The present invention relates to a semiconductor device wherein semiconductor chips are electrically connected to a wiring board and sealed, and a manufacturing method thereof.
In a conventional semiconductor device, a plurality of circuit wirings are provided on a front surface of a wiring board formed of a glass epoxy resin. Semiconductor chips are electrically connected to the circuit wirings and mounted thereto. The semiconductor chips mounted onto the wiring board are sealed with a first encapsulating resin layer such as a resin approximately equal to the wiring board in thermal expansion coefficient. The first encapsulating resin layer is heated and temporarily cured. After the temporary curing of the first encapsulating resin layer, a second encapsulating resin layer comprised of a high Tg resin made coincident with the wiring board in thermal expansion coefficient is applied so as to reach a thickness similar to that of the wiring board. Then, the first and second encapsulating resin layers are heat and cured and external terminals are formed on the back surface of the wiring board, whereby the above semiconductor device is manufactured. Excessive thermal expansion of the first encapsulating resin layer exceeding a glass transition temperature Tg upon heat treatment in a reflow process at the mounting of the semiconductor device on a mounting board is suppressed by the second encapsulating resin layer which does not exceed the glass transition temperature Tg, thereby preventing warpage of the semiconductor device.
After the temporary curing of the first encapsulating resin layer, a high rigidity member comprised of a metal or the like smaller than a range in which a resin encapsulating layer is applied is disposed on the first encapsulating resin layer. Thereafter, the second encapsulating resin layer is applied and thermoset to enhance the rigidity of the semiconductor device, thereby preventing the warpage of the semiconductor device in the reflow process (refer to, for example, a patent document 1 (Japanese Unexamined Patent Publication No. Hei 10-112515 (paragraph 0019 in page 4 to paragraph 0031 in page 5 and paragraphs 0031 to 0033 in page 5, and FIGS. 1 and 3)).
In the above patent document 1, the semiconductor chips mounted on the wiring board formed of the glass epoxy resin are sealed with the encapsulating resin layer approximately equal to the wiring board in thermal expansion coefficient. Therefore, even though the encapsulating resin layer is heated and cured in the sealing process step, no warpage occurs at that time, whereas when the thermal expansion coefficient of the wiring board is smaller than that of the encapsulating resin layer, warpage caused by the difference in thermal expansion coefficient at the cooling subsequent to the heating/curing of the encapsulating resin layer in the sealing process step, that is, dish-shaped warpage occurs due to more shrinkage of the encapsulating resin layer at the cooling subsequent to the heating/cooling.
In order to prevent such dish-shaped warpage, the present applicant has proposed a technique wherein in Japanese patent application No. 2005-87644, when semiconductor chips are mounted on a wiring board such as a silicon substrate small in thermal expansion coefficient and sealed with an encapsulating resin layer, a metal plate or sheet formed of a material having a thermal expansion coefficient approximately equal to that of a silicon substrate or the like such as a metal plate is provided on the opposite side of the silicon substrate or the like to thereby prevent the dish-shaped warpage of the semiconductor device.
Incidentally, the high rigidity member formed of the metal or the like (having about half length according to FIG. 3 of the patent document 1) smaller than the range in which the encapsulating resin layer is applied, is disposed on the first encapsulating resin layer after the temporary curing of the first encapsulating resin layer in the above patent document 1. Therefore, even though the second encapsulating resin layer is thereafter applied and thermoset, the wiring board and the high rigidity member are set to the same degree in the amount of shrinkage because the length of the high rigidity member less than or equal to half in thermal expansion coefficient is set to about half the length of the wiring board, thus causing no problem referred to above.
However, the patent document 1 is accompanied by problems that when the technique of the patent document 1 is used in the semiconductor device in which there is the difference in thermal expansion coefficient between the wiring board and the encapsulating resin layer, more warpage occurs on the shrunk side at the cooling subsequent to the heat treatment for heating/curing when the wiring board equipped with the semiconductor chips is sealed with the encapsulating resin layer in the sealing process step at its manufacture and it is heated/cured and cooled, and when the thermal expansion coefficient of the wiring board is smaller than that of the encapsulating resin layer, the dish-shaped warpage occurs, whereas when the thermal expansion coefficient of the wiring board is large than it, shallow bell-shaped warpage occurs.
With the occurrence of such warpage, the wiring board or the like cannot be held reliably when the wiring board formed with the encapsulating resin layer is held on a working table or the like by suction under vacuum in the external terminal forming process step subsequent to the sealing process step. Further, the formation of the external terminals might become difficult. When the wiring board or the like is held on the working table or the like by a mechanical clamp apparatus, cracks occur in the wiring board or the like because the force trying to correct the warpage acts.
This occurs even in a dividing process step at the time that a plurality of semiconductor devices are simultaneously formed and divided into fractions or pieces. Their retention might be incomplete when they are applied onto a dicing sheet having adhesion to divide them into the fractions.
The above results in a reduction in the manufacturing efficiency of the semiconductor device.